1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a DRAM capacitor.
2. Discussion of the Background
Dynamic random access memory chips, or DRAMs are applied broadly in the field of integrated circuits devices, and more importantly, in the electronics industry. DRAMs with higher capacitance are necessary for the development of the industry. As a result, DRAMs with higher density and capacitance are of great interest and are developed by the related industry. Maintaining quality as the size of these devices is reduced is now a task for the industry to overcome.
In digital data storage, the capacitance of the memory is called a "bit" and the unit for data storage in a memory is called a "memory cell". The memory cell is arranged in an array consisting of columns and rows. A set of a column indicator and a row indicator represents a specific address. Memory cells in the same column or the same row are coupled by a common wiring line, which is called a word line. The vertical wiring line related to data transmittance is called a bit line. The current design of DRAM is composed of a transistor which is series-coupled to a capacitor to replace the original memory consisting of three transistors. In this manner, the circuit is simplified and the density of the device can be increased.
For the design of Ultra Large Scale Integration (ULSI) DRAM, the lithography and alignment controlling the contact is increasingly more and more critical as the device size is gradually reduced. Currently, the minimum diameter of the node contact hole is 0.24 .mu.m. When the photolithography step is performed to define a node contact hole, the node contact hole must align with the source/drain region. The larger the node contact hole is, the less tolerance for the contact hole the source/drain region has. The lower tolerance of the source/drain region for the node contact hole results in the decrease of the alignment accuracy. Accordingly, the node contact is easily electrically coupled to the bit line surrounding the node contact, and this causes device failure.
In order to improve the alignment accuracy, the surface area of the source/drain region is expanded to enhance the allowance tolerance range for the node contact hole. But the expansion of the surface area of the source/drain region lead to the enhancement of the junction capacitance. Moreover, the enhancement of junction capacitance slow down the transportation rate of the transistor.
FIGS. 1A through 1B are schematic, cross-sectional views of the x-axis of a DRAM capacitor undergoing manufacturer by a conventional process.
First, as shown in FIG. 1A, a substrate 100 having a word line 104 and a source/drain region 102 is provided. An insulator layer 110 is formed to cover the substrate, and then a bit line 106 is formed by patterning the insulator layer 110. Next, an insulator layer 108 is formed to cover the substrate. For the sake of simplicity, an insulator layer 108b is thus formed and comprises the insulator layer 110 and 108. A hard mask layer 112 such as a silicon nitride layer is formed on the insulator layer 108b after the insulator layer 108b has been planarized.
Referring to FIG. 1B, the hard mask layer 112 and the insulator layer 108b are patterned to form a node contact hole 114 until the node contact hole exposes a portion of the source/drain region 102. The insulator layer 108b and the hard mask layer 112 are converted into an insulator layer 108a and a hard mask layer 112a.
FIG. 2 is a schematic, cross-sectional view of the y-axis of the FIG. 1B. In order to increase the integration of the ICs, the distance between the bit line and the word line is reduced. The minimum diameter of the node contact hole manufactured by using conventional techniques is 0.24 .mu.m, so that the allowance tolerance range of the source/drain region for the node contact hole is reduced. Therefore, the alignment accuracy is decreased. Due to the decreased alignment accuracy, the node contact subsequently formed easily becomes electrically coupled to the bit line 106 surrounding the node contact. Consequently device failure is caused because the node contact is electrically coupled to the bit line.